S0-S1
A processor
chip's byte code Sequencer stride registers address
registers.
SCA
Single Connector Attachment is an 80-pin backplane connector
for the Parallel SCSI bus (rather than using ribbon
connectors) in a multi-drive cabinet typical of SCSI-based
RAID drives.
SCAM
SCSI Configured Auto-Magically supports hot-plugging&emdash;plugging or unplugging a device while the power is on&emdash;with automatic bus configuration. The SCSI-3 parallel standard implementation enables software to control the automatic assignment of SCSI IDs to individual devices.
SCR
These are referenced with other Diodes.
SCSI
The maximum data transfer rate for both SCSI-1 and -2 is 5 MBps (megabytes per second). There are fast, wide, and fast and wide SCSI -2 implementations. "Fast" is a doubling of SCSI's data transfer rate by bursting data to higher speeds (without changing the bandwidth). Wide is doubling SCSI's bus from 8-bit to 16-bit or 32-bit. The fast SCSI-2 doubles SCSI's data transfer rate bursting data at 10 Mbps (without changes in bandwidth).
The wide SCSI-2 uses a wider data path&emdash;16 bit rather than the normal 8 bit&emdash;for the same 10 Mbps. Combining both fast and wide can, in theory, reach 20 Mbps. Expanding the wide from 16 bit to 32 bit together with the fast implementation could result in a 40 Mbps data transfer rate.
SCSI "Ultra" (or "Fast-20") specification is a subset of SCSI-3, which was developed to provide 40 Mbps through a 16 bit bus. (With a maximum 20 megatransfers during an I/O operation, the larger the block (bytes), the faster the transfer.)
SCSI-3 supports all previous specifications and is downward compatible with SCSI-1 and -2 devices, operating systems and software. It also expands support to 15 daisy-chained devices and supports implementation of a serial fiber-optic cable interface for 1 Gbps data transfers.
SCSI-2 requires shielded cables with Centronics-50 or high-density SCSI-2 to Centronics-50 connectors. (Some implementations use dual cables; a 50-pin cable for 8-bit transfer, and a 60-pin cable for 24-bit transfers.) Both 16-bit and fast 16-bit SCSI require single high density cables with 68-pin "P" connectors. Fast-wide 32-bit SCSI-2 data transfers requires two cables with Centronics-50 connectorss (for maximum speed).
SCSI-3 parallel uses either a high-density SCSI-2 or SCSI-3 (P) cable. Serial SCSI-3 (SSI), also known as Serial SCSI Archecture (SSA), use both fiber-optic and copper-wire cables. Note: PC What's The Problem includes functional troubleshooting suggestions.
SCSI cabeling. The 8-bit, and fast 8-bit SCSI-1 use cables with Centronics-50 or SCSI Alternative-2 to DB-25 or Centronics-50 connectors to link the first device to the host. Cables with Centronics-50 or SCSI Alternative-2 to DB-25 or Centronics-50 or 26-pin IDC connectors to link one device to another.
"Ultra" was defined in the SCSI-3 standards documentation, (FAST-20, X3T10/1071D). The tolerance for Ultra cable impedance (84 to 96 ohms ) is within the the original SCSI impedance range (72 to 96 Ohms).
The typical implementation for high-quality cables is Ohms from high 80s to low 90s. While there are no hard limits for length, load and spacing, most implementations have a maximum length of 3 meters (3 m) of daisy-chained cables connecting a maximum or 4 equally spaced devices, or a maximum length of 1.5 m with a maximum of 8 equally spaced devices. Implementations that use Incident-Wave Switching rather than the original Reflected-Wave Switching can extend the limits of the SCSI bus. For example, a 16-bit wide single-ended SCSI bus with 6m of cable servicing 16 devices.
Cable length can be extended to 25 m while improving signal quality using Differential parallel signal transceivers (or transmitters and receivers) rather than using the single-ended method. A refinement, the universal low-voltage differential (LVD) method extends cable lengths while increasing transmission speeds.
Other enhancements include the use of Extenders, Regenerators, Converters and an Enhanced Parallel Interface (EPI) also known as an Expander.
All SCSI and SCSI-2 interfaced drives are compatible with MacOS systems&emdash;with the proper cable connectors and device-driver software. Each MacOS system has an external DB 25-pin cable socket which is similar to, but not compatible with, an RS-232's interface. Internally, each MacOS system has the standard 50-pin centronics-type cable socket. All SCSI drives and devices have 50-pin cable sockets. The data transfer rate of SCSI drives is dependent upon the SCSI controller chip inside the computer. The maximum rate ranges from 1.5 MBps, for the older MacOS systems (with either the NCR 5380 or 53C80 SCSI controller chip), to 3.2 MBps for the Quadras (with an NCR 53C90 chip) and higher for PowerPC-based systems. For best performance, the drive and driver should be able to use the advanced features of MacOS's latest SCSI Manager.
Note: PC What's The Problem? includes functional troubleshooting suggestions.
SCSI-D SCSI-diff is a
A SCSI-interface bus with a differential encoding transceiver--for longer distances--up to 25 meters. Differential SCSI measures the difference between the voltages of two series of ground wires; standard-length single-ended SCSI measures the voltage changes of a single series of ground wires. The SCSI-D bus has different signal-pin assignments than the standard bus; although their cable interfaces are identical. Because of this incompatibility, to interconnect the two types of busses, a SCSI bus converter is required.
SCSI-F or SCSI-fast
A Fast SCSI-2 interface that sends data at 10MBps. Fast-20 SCSI (or Ultra-SCSI) achieves 20MBps on 8-bit SCSI cable, 40MBps on Wide 16-bit cable; and doubles these speeds in burst mode to a 80MBps.
SCSI-W or SCSI-wide
A Wide SCSI-2 interface that increases the data bus to 16- or 32-bit. Wide transfers doubles and quadruples the data sent with each handshake.
SDLC
Synchronous data link control. Refer to Synchronous Communications.
SDRAM
Synchronous Dynamic RAM chips use synchronous operation, pipelining, burst mode and command storage registers to support 100 MHz CPUs without cache and wait states. SDRAMs have a synchronous, clocked interface that is faster than the asynchronous interface of other types of DRAM which also don't have clock input. Using concurrent page-mode access, pages in each of a SDRAM's two cell banks can be accessed as if they were separate RAM chips. For example, a cell in one bank can be written to while a cell in another bank is read from&emdash;simultaneously! And pipelining, after a first read cycle, conducts the address input and data output delays of subsequent cycles concurrently.
If a SDRAM is internally programed for burst-mode data-transfers, once a column address for the first memory location is set by the Internal Column Address Generator (ICAG), subsequent addresses will be automatically generated&emdash;either interleaved (for Intel CPUs) or sequentially (for Motorola CPUs). The number of words in each burst may be programed for either data reads or writes. To optimize SDRAM performance and define column-address strobe latency, the burst type and length desired, addressing mode, test mode, etc., the command storage registers are loaded with the system's configuration.
SDRAM's support of two accesses at the same time, makes it ideal for computers with bus speeds of 66MHz or faster; such as, those with the 350MHz Pentium II, AMD's K6 3-D, Cyrix's 6x86MX and AIM's (Apple-Intel-Motorola's) PPC 750 processors. The "common guidelines" for Intel-based systemboards with 66MHz and 100MHz bus speeds are the PC 66 and PC 100 specifications. Because of systemboard, processor and memory module requirements, use only SDRAMs that match the systemboard's bus speed. Another reference: DDR.
Sectors Per Track ( spt ).
In a stationary position, a read-write head traces a full circular-track across a platter's side when the disk makes one complete rotation. Platter sides have many concentric tracks filling the area between its hub and outer rim. Each circular-track is further divided into short arcs called sectors by the low-level formatting software. In a typical hard drive, all of the platter sides have the same number of circular-tracks and sectors; however, there are some drives that have variable sectors per track (v-spt). Sectors are determined by the drive's data-storage encoding method.
The standard, MFM (Modified Frequency Modulation) provides 17 sectors per track; RLL (Run Length Limited) and other encoding methods can fit 35 or more sectors per track. Sectors start from the number 1. The standard DOS capacity per sector is 512 bytes; however some manufacturers have set capacities of 256 or even 1,024 bytes per sector (bps) for some of their drives. Areal recording density is the bit density multiplied by the track density: the number of bits per inch (bpi) of track-0, multiplied by the number of tracks per inch (tpi) from hub to rim, results in the number of bits per square inch. (Track-0, the first track out from the hub, has the smallest circumference and therefore the most densily-packed sectors.)
Seek or sk.
Many manufacturers only provide the drive's seek time instead of its average access (AA) specification (which includes the drive's spinning rotational latency-time).This performance specification may be the average track-to-track and/or the full-stroke seek time (seeks between the highest and lowest cylinder). Seek times for translated drives (IDE and EIDE) usually do not include the translation time between the logical and physical.
SEQ
Sequencer programmable control unit inside a (RISC) processor chip which operates the Arithmetic Unit.
Serial cables
Two devices are connected together so that data can be transfered between them. They are termed "serial" because they send one bit at-a-time via a single (pin #2) wire within the cable and receive it via another (pin #3); although, secondary wires (pin #s 14 and 16) may also be used for these functions.
Servo Motor
A small motor with many applications; for ecample: In a hard drive, it moves the read/write heads, on command, to specified locations above the spinning data-storage media (disks).
It moves a Satellite Dish's Feed Horn so that it can be oriented to the polarity of the satellite signal for capture and channeling of the signals to the LNB amplifier located in the front-end of the satellite system.
SGRAM
Synchronous Graphics RAM chips are a variation of the SDRAM. It has a x32 organization and VRAMlike pixel-processing features. Like SDRAM, it allows two accesses at-a-time but adds graphics capabilities; however, it doesn't have the bandwidth to allow resolutions needed for high-end graphics (millions of colors at resolutions higher than 1,024 x 768 pixels). These chips are used in the Power Macintosh G3.
Short Circuit
The condition when two wires are touching in a cable circuit due to damaged or missing insulation, or an open break in the wire. A short circuit can also be created when a circuit is completed at a point too close to the origin, often resulting in power surges and damage to the device.
Signal-Noise Ratio or "S/N"
A communication channel is rated by the amount of signal power (in decibels "dB," a voltage-level measurement) it can handle compared to the detected (errors) "noise" generated. For phone lines, the "S/N" ratio is 20 dB. A standard (non-leased) telephone line, has a bandwidth of about 3,000 Hz. This permits a maximum data transmission of approximately 24-Kbps (kilo-bits per second); however, phone companies may limit signal bandwidth so they can multiplex&emdash;send many signals (piggybacked on top of each other) simultaneously.
A 300 bps transmission rate, using FSK modulation, requires a 600 Hz bandwidth; two carrier signals at this rate would double the required bandwidth to 1200 Hz. Full duplex (simultaneous two-way) transmission doubles bandwidth requirements. For example, 9.6-Kbps x 2 (full duplex) equals 19.2-Kbps. High speed transmission on phone lines should not approach the functional limits. The S/N
of a standard line significantly decreases the rate data is received; errors require more repeat transmissions. Modems are rated for their bit-error-rate (BER) which is contrasted to the wire's S/N ratio. For high speed, choose leased phone lines and/or ISDN or even V-standard modems.
SIF
Standard Image Format for composite color video in the USA is a 320 by 240 pixel image, as stipulated by the NTSC (National Television System Committee). In Europe it is a 384 by 288 pixel image, as stipulated by the PAL (Phase-alternation line) standard. Compare with CCIR, CIF, QCIF, and QSIF.
SIMM
Single In-line Memory Module packaging have groups of chips soldered onto a small circuitboard, approximately 3 inches long, either by the DIP or surface mounted device (SMD) process (described in Section 20). A SIMM looks like a SIP board but instead of the comb-like row of pin-leads, a SIMM has a single row of flat rectangle-shaped contacts along its bottom edge which plug into a special socket on a systemboard or system-expansion board.
SIMM are available in a wide range of capacities from 256K to larger than 128MB. SIMMs have a density of "X" bytes (B). The chips which make up a SIMM have a width of "X" bits (b). (1 Byte = 8 bits; the capacity required to store a character, i.e., a letter, digit, punctuation mark, etc.
Whatever the number of chips or individual capacity (1 megabit, 4 megabit, etc.), a complete SIMM must have 8-bits of width or a multiple of 8 (8-bit, 16-bit, 32-bit or 32-bit). SIMMs may have different shapes and chip arrangements. For example, Composite SIMMs reduce costs and achieve greater capacities by using a greater number of lower density chips.
Consider a standard 16MB SIMM, it would probably have eight 16Mb chips (plus a parity chip if required). A 16MB Composite SIMM might be constructed using thirty-two 4Mb chips with some additional logic to make the computer see the SIMM as a standard piece of memory. However, the greater number of chips can affect a SIMM's reliability, so purchase them only from a company with a history of building them correctly. There are three physical classes of SIMM:
The first includes the Surface Mounted Device (SMD) SIMMs. There are two construction types of these low profile SMD-SIMMs: lower-capacity Plastic Leaded Contact Chip (PLCC), or higher-capacity Single Out-line JLead (SOJ).
Second, the Dual in-line package (DIP) SIMMs, have a relatively low-cost pin-through-circuit board-hole design (like RAM chips soldered into a board). Their higher profiles require widely-spaced socket arrangements.
Piggyback SIMMs, the third type, are the most expensive. These SIMMs themselves are socketed into which another SIMM may be inserted&emdash;one on top of the other. This arrangement lets a single socket on a systemboard or expansion-board access two SIMMs. A system's RAM capacity may be expanded beyond the originally stated physical capacities of the board.
Note: PC What's The Problem? includes identification, test, and replacement suggestions.
SIMM banks
Banks have one or more SIMM sockets logically connected. Some systemboards have one bank, while others have two, four, six, or eight banks. The number of SIMM sockets in a Bank is determined by the CPU in the system, its datapath and the SIMM sockets. For example, a CPU with a 32-bit wide datapath can send or receive data 32 bits at a time. If the SIMM sockets require 30-pin SIMMs, each will be either 8-bits or 9-bits wide whether the SIMM is 1MB, 4MB, 8MB or greater. It takes 4 of these 8-bit SIMMs working together to achieve 32-bits of width; therefore, four 30-pin SIMM sockets would comprise a bank. If the SIMM sockets require 72-pin SIMMs, each will be either a 32-bits or 36-bits wide regardless of its capacity; therefore a bank in a system with a CPU that has 32-bit wide datapath is only one SIMM. If the CPU has a 64-bit datapath, there will be two 72-pin SIMMs in a bank.
Other considerations:
a) Each SIMM within a bank must have the same capacity, four
1MB SIMMs, four 4MB SIMMs, etc.
b) Many systems require banks to be filled in alphabetical
order, A, B, C, etc.
c) Many systems support the use of SIMMs with different
capacities in different banks. but, they may require a
reordering of the banks; e.g., bank-A having SIMMs with less
capacity than bank-B, and so on. (The reverse order may be
true too.) d)
Like individual chips, SIMMs are rated by their minimum processing speeds; the lower the nanosecond number (150-, 120-, 100-, 80-, 70-ns), the faster the chip. If any of the installed SIMMs have a different speed (in nanoseconds), all banks will function at same speed as the slowest SIMM&emdash;as long as that speed is supported. SIMMs slower than the system's minimum requirement will not be recognized and will probably cause the system to crash. e) If the system requires parity error checking, make sure all SIMMs have either the extra chip or otherwise includes this capability.
SIP
In Single In-line Packaging, groups of RAM chips are soldered on a small board either by the DIP process or surface mounting SMD process. The board itself has a single row of pin-leads (like a comb) extending from its bottom edge, which plug into a special socket on a system- or system-expansion board.
SMD-E and SMD-H
Storage Module Device drive interfaces are typically used by power-hungry 8-inch drives with capacities greater than 2GB. These minicomputer and workstation drives require a separate intelligent drive controllerboard. The SMD interface uses separate control and data cables to daisy chain up to 4 devices (including the computer). The data transfer rate is 3 Mbps.
SODIMM
Small outline dual inline memory module are designed for applications with limited space and require low power consumption.
SPI
Sequencer Processor Interface inside a (RISC) processor.
SPR
Symmetric Phase Recording, developed by Quantum Corp., packs data across a tape's recording surface by writing adjacent tracks in a herringbone pattern: track 0 = \\\\\, track 1 = /////, track 2 = \\\\\, track 3 = /////, etc. This eliminates crosstrack interference and guard bands so that more tracks of data can be stored on a tape.
SR
Inside a processor, the Status Register.
SRAM (Static RAM) chips
They store bits in cells that act like electronic switches reflecting their logic state, either ON for logic 1 or OFF for logic 0. When power is received, all SRAM cells are ON (in a logical 1 state). Subsequent data writing to the SRAM may change some of its cells to a logical 0. This state is maintained until the next write operation or when power is removed. Maintaining a SRAM's static state requires more power than the constant refreshing of a DRAM. However, SRAM is considered almost non-volatile, requiring such little power that a minature battery can keep data stored in it active for several months. It is the choice of most system desigers for use as Cache RAM. SRAM is faster than regular DRAM, which makes it way more expensive. They are often used in Level 2 caches. Note: PC What's The Problem includes functional troubleshooting suggestions.
SRDRAM
Self-refreshing DRAM is a variety of DRAM that draws less power than the standard DRAM chips. It is most often used in low-power notebook computers. Most manufacturers specify single memory modules, or boards with TSOP chips. A few specify modules with VTSOP-type chips.
SRF
Inside a processor, the Status Register File.
ss -
Label indicates a single sided disk, cartridge or CD stores data on one or its two surfaces epitomized for this purpose.
SSA
Serial Storage Archecture interface which uses SCSI-3 specifications.
SSFDC
The solidstate flopy disk card is also known as the SmartMedia card. It consists of a 37-by-45 mm card that is either 0.75 or 1.4-mm thick. The SSFDC employs a double-row 22-contact interface intended for byte-serial data transfers, such as from NAND-based flash RAM. A write-protect mechansim prevents accidental writes. The card was originally designed to store camera images and transport them to a computer. An 8 MB disk is capable of storing 40 still images at two images per second.
SSI Serial SCSI-3 interfaces
SSI includes: SSA-P1394 "FireWire," SSA-Fiber Channel, and Fiber Channel-A. It can use 20m serial cables and support up to 127 devices (at 20MBps). Fibre Channel-Arbitrated Loop (FC-AL) transfers 100 MBps or 200 MBps using a dual loop configuration. Up to 126 devices can be connected to the host adapter; distances are based on the cable used: 30 m using coaxial cable, 100 m via a backplane (copper cable), and a maximum 10 Km with fiber optic cables. There are two newer specifications: SSA and P-1394. Serial Storage Archecture (SSA) is a drive interface with great potential.
Stepper Motor (SM)
Motor turns a mechanical screw which "steps" a drive's actuator-arm, one-track-at-a-time to the specified read/write position. You can hear a soft "buzz" or "beep" each time the motor turns the screw, on-off, on-off... moving the actuator-arm's read/write head track to track.
Supply voltage
Usualy labeled as VDD, a circuit's supply voltage is determined by the circuit or the designer. For example, most desktop computer systemboards use 5VDC (5 volts direct current); while most laptop computer systemboards use 3.3VDC.
Switch Box or switchbox
The simplest type of switch box requires that a selection knob be manually turned. There are many versions of this type of device; however their common purpose is to let several devices share a common interface. Several devices, such as computers, may be linked to single device such as a printer. A switch box termed as: "2 by 1," has two settings; an "A" and "B" switch position; either device A, or device B may access device "C."
Some switch boxes offer dual male and female interfaces. A 2 by 1 dual switch box would permit the use of either a male, or female "A" setting; either a male or female "B" setting; with either the A- or B-connected device accessing the C-interfaced device (which may also be either male, or female). The only cables permitted are an A, a B, and a C; but, they may be plugged into either the male or female interface depending on the cable's connector. Other than this type of switch box, almost all other switch boxes have only female interfaces.
One or more devices, such as computers may be linked to one or more other devices, such as printers, (usually two of each, which would be termed a "2 by 2"). These "2 by 2" switch boxes are of two versions: A or B connects with either: C or D; connect: A with either: C, D, or B. Fig. 1, shows a Loop Back switch which permits two terminals, or (data terminal equipment, "DTEs"), or modems (data communications equipment, "DCE") to communicate one to the other.
Some switchboxes act as adapters between different interfaces such as a Modem Substitution Switchbox. A "2 by 1" box, of this type, has three RJ-11, and three DB-25 interfaces. You may switch between two modems where there is only one RJ-11 plug; or, you may switch between two modems which may have different speeds, or phone line access, etc.
SWX
Switch. The crossbar switch within a (RISC) processors's Arithmetic Unit that connects the ACM to SEQ, VMP, DTU, and AP.
Synchronous communications.
While asynchronous communications frames each character, synchronous communications uses only one set of controls to frame the "block" (or "field") of data which may vary in size from zero data bits up to the limits of memory and protocol specifications. The proportion of data to control information is therefore far greater for synchronous transmission. The data-block plus it's framing control information is considered a "Frame."
Note, Hayes® AT commands cannot be issued in synchronous mode. Instead, use V.25bis to initiate calls, if it is an option. There are three different synchronous framing protocols: SDLC (synchronous data link control), BSC "bisync" (binary synchronous communications), and HDLC (high-level data link).
The BSC protocol is a character-based modem protocol for half-duplex link operation which may include pauses in transmission. (IBM™ has functionally replaced it with its bit-oriented SDLC.)
The SDLC and HDLC data-block is composed of a stream of binary numbers without character boundaries, representing both characters and non-characters. While BSC may include pauses in the transmission of a data-block, SDLC/HDLC sends the block in a continuous stream. First a Data Start Flag, then 8-bit control and address "fields" are sent. Next the data block, followed by CRC (Cyclical Redundancy Check) bits and last, the Data End Flag. HDLC adds an extra address field, a packet header, so that packet-switching LANs can route the frame to the proper destination.
Synchronous Connection
An analog to analog or digital to digital connection that is able to perform two or more processes at the same time by means of a mutual timing signal or clock.
References are samples only. Each one is presented in greater detail in the
Technical Research Assistant 2001
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Did you find any Inaccuracies?
Your EMAIL comments are invited
on CD in Adobe Acrobat PDF format
Book
Visit our
Enter the library through its Opening page
All rights reserved.
to top